The present invention relates to a semicondutor memory device. More particularly, the present invention relates to a DRAM memory device provided with capacitors formed above and below a cell transitor, and a method for its manufacture.
Recently, there have been many studies for improving the structure of a stacked capacitor cell and a trench capacitor cell for DRAM devices of 256 Mb and beyond. However, it is still very difficult, despite an extremely complicated manufacture process, to ensure sufficient cell capacitance in DRAM cell having a 1.5 V operation voltage and 0.5 .mu.m.sup.2 cell size.
Further, in a layout having sufficient alignment margin, either the cell having a feature size smaller than the current minimum feature size, or the storage electrode must have a height larger than the current height. The small cell size is almost impossible to obtain because of limits in current photo-etching processes, and the increased storage electrode-height problem in manufacturing.
In addition, as the impurity concentration of the source and drain of the metal-oxide semiconductor (MOS) device becomes high, the junction leakage current gradually becomes larger, thereby causing data storage problems.
FIGS. 1A-1E are section views showing a method for manufacturing a DRAM having a buried capacitor (see "A Buried Capacitor DRAM Cell with Bonded SOI for 256M and 1 Gbit DRAMs" by Toshiyuki Nishihara et al., IDEM, 1992, pp803-806), for solving the above-described problems.
Here, a trench for forming a cell separating insulation film is formed on silicon substrate 500, and SiO.sub.2 film is deposited thereon and etched, to thereby form cell-separating insulation film 502. Subsequently, polysilicon/SiO.sub.2 pillars 504 are formed in order to form a storage electrode connected to the substrate. Meanwhile, in a peripheral region, i.e., the region where the storage electrode is not formed, dummy patterns 505 are formed to compensate for the height of pillars 504 (FIG. 1A).
Next, polysilicon is deposited all over the resultant structure on which the pillars and dummy patterns are formed. Then, the polysilicon is etched back, to thereby form spacer 506 on the sidewalls of the pillars (FIG. 1B).
After the peripheral region is covered with photoresist pattern 508, the SiO.sub.2 portion of each pillar is removed using HF solution. As a result, 1.6 .mu.m-high storage electrode 510 is formed (FIG. 1C).
A dielectric film 512 and plate electrode 514 are then formed. Subsequently, polysilicon buffering layer 516 is deposited and etched back, to thereby planarize the surface thereof. Then, support wafer 518 is bonded to the buffering layer 516 (FIG. 1D).
Lastly, the rear surface of silicon substrate 500 is polished, thereby leaving active region 520 of 80 nm between each cell-separating insulation film 502 (FIG. 1E).
According to the above disclosure, a cell capacitor is formed below an active region and completely buried so that the degree of planarization of a word line and bit line formed in a subsequent process can be improved. In addition, the margin for forming a storage electrode is slightly increased. However, there are certain drawbacks to this method.
First, for the case of a cylindrical storage electrode, the height of the storage electrode has to be above 1.5 .mu.m in order to ensure sufficient cell capacitance with the limited cell size.
Second, the process becomes more difficult because a dummy pattern is needed.
Third, since a contact hole for connecting a storage electrode to an active region and a contact hole for connecting a bit line to an active region are formed together in a limited active region, the contact hole size and channel length are reduced. As a result, contact resistance increase and a short channel pattern are generated, which may cause a serious problem in the operation of the device.
Fourth, if a storage electrode that repeats charge/discharge is formed above a transistor, operational characteristics of the transistor are unstable due to the charge/discharge. Therefore, it is desirable to form a storage electrode avoiding the region where the transistor is to be formed. As for the Nishihara et al. invention, when a folded bit line structure (where a bit line is formed lengthwise and a word line is formed crosswise of an active region) is adopted to stabilize operational characteristics of the transistor, cell size in the word line direction becomes 0.3 .mu.m to 0.4 .mu.m. Thus, an area occupied by a cell capacitor becomes extremely small, which causes great difficulty in ensuring sufficient cell capacitance. Accordingly, to ensure sufficient cell capacitance, a more complicated process is needed or the storage electrode height has to be increased.